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  Synopsys DC-T培训
   入学要求

        学员学习本课程应具备下列基础知识:
        ◆ 电路系统的基本概念。

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       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【北京分部】:北京中山学院/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦 【石家庄分部】:河北科技大学/瑞景大厦
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  Synopsys DC-T培训
培训方式以讲课和实验穿插进行

课程描述:

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Overview

This workshop familiarizes you with the physical constraints that enable the strong DC-T correlation with physical tools. Through a combination of class lecture and hands-on labs, you will learn what the physical constraints are, how to load them into DC-T, how to view them, and how to verify they are complete and correct.

As part of the set up and run methodology, you will generate scripts using the Reference Methodology Script Generator (RMgen), and will adapt them to your design.

This workshop covers typical flows (flat, both with and without a floorplan, and hierarchical). It describes how the power and test flows fit into the DC-T flows. It covers methodologies that are common across all flows.

This workshop shows you how to setup for, analyze, and handle congestion, using text reports to quantify the congestion, and using the GUI to qualify it.

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Objectives

At the end of this workshop the student should be able to:

  • Load the physical input files to DC-T and list the actions to be taken on them
  • Configure and generate RMgen “seed scripts” ,??and adapt those scripts to your design
  • Understand three frequently-used DC-T flows:

·???Classic flat with Power and Test with a floorplan

·???Classic flat with Power and Test without a floorplan

·??Hierarchical

  • Use methodologies common to all flows
  • Navigate the GUI to explore a floorplan
  • Set up for the most accurate congestion analysis
  • Analyze congestion using both text and GUI
  • Recommend congestion fixes

Audience Profile

Engineers familiar with Design Compiler using wire load models.

Prerequisites

To benefit the most from the material presented in this workshop, students should:

●?Have taken the Design Compiler 1 Workshop

Course Outline

Unit 1

·??Physical Elements

·??Set up and Run

·??Common Flows

·??Congestion

Unit 2

???DC Synthesis and optimization techniques, questions and answers